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Need a consistent naming convention on variables #146
Description
IMO, a consistent coding style, including naming convention, is important for good code.
While starting my own Chisel project some time ago, I faced some port mismatch issues, and found it was caused by inconsistent port naming. I then traced my study history back to this repository.
Long story short, here are the examples:
- Many codes use TitleCase naming on ports, such as https://github.com/ucb-bar/chisel-tutorial/blob/release/src/main/scala/examples/Adder4.scala
- Some codes use lowerCamelCase naming on ports, such as https://github.com/ucb-bar/chisel-tutorial/blob/release/src/main/scala/examples/FullAdder.scala
I think we need some guideline on this, for example ScalaStyle?
Activity
edwardcwang commentedon Mar 26, 2019
Thank you for your interest in Chisel!
There is a style guide for Chisel itself here: https://github.com/freechipsproject/chisel3/blob/master/doc/style.md
From my experience, usually ports are either
camelCaseorsnake_case(inherited from Verilog). I would also note that coding/naming styles do vary across institutions depending on the nature of the group/team.Finally, have you seen https://github.com/freechipsproject/chisel-bootcamp ? The Chisel bootcamp is our latest iteration of Chisel educational materials.